A new generalized switched diode multilevel inverter topology with reduced switch count and voltage on switches

摘要

This article presents a new multilevel inverter topology with reduced power switches. The proposed topology composes of several series connection of basic unit for obtaining a required output voltage level. The proposed topology can operate in symmetric condition. The proposed topology is connected in a cascaded structure to produce a higher number of output voltage levels. The proposed cascaded structure is optimized with the minimum number of components for the maximum number of levels. To prove the superiority of the proposed multilevel inverter topology, different technical parameter comparisons are carried out with recently developed multilevel inverter topologies from the literature. The calculation of total standing voltage is examined for the proposed topology. The operation of the proposed topology is tested and verified for nine-level output voltage. The simulated results are carried out, and it is strengthened by the real-time prototype results.