Real-time Hardware Implementation of Stereo Image Rectification with Calibrated Cameras

摘要

Nowadays stereo matching has been proved as a useful technique for acquiring depth information from stereo images. To reduce the computation cost of the matching process, image rectification is regarded as an essential step which horizontally aligns the objects in both images. However, it is still a challenge to reach good performance in both processing speed and rectification quality. In this paper, the whole rectification process can be divided into two phases, which are implemented by a core processor and dedicated hardware separately. A hardware architecture is proposed based on the rectification method. Furthermore, the architecture is optimized as a pipelined system to improve its processing ability. In the system which is implemented on an Altera FPGA, real-world images are captured by calibrated cameras as input, and rectified images of 1024 × 768 resolution are displayed as output at 60 frames per second (fps). The experimental results indicate that the rectified images have few pixels of vertical mismatches.