Performance Enhancement of Full Adder Circuit: Current Mode Operated Majority Function Based Design

摘要

Paper reports a novel majority function based current mode operated compact sized robust design of 1 -bit full adder (FA) circuit. The focus of this work is to reduce the power supply consumption required for performing arithmetic operations by introducing a novel and efficient way of computing 1-bit addition relying on current mode operation. Presented high speed FA design utilizes only 7Ts, per bit, to implement sum and carry functions. The majority function based proposed FA circuit requires lesser number of transistors as compared to the conventional 28Ts FA circuit. A current mirror (CM) circuit has been incorporated in the proposed design to act as a constant current reference to drive the whole circuitry. Further, to evince the uniqueness of the proposed FA design, comparisons have been drawn with various other standard FA designs in terms of different design metrics such as power consumption, supply voltage requirement, power delay product (PDP), energy delay product (EDP) and operating speed. Extensive simulations have been performed using Virtuoso Analog Design Environment of Cadence @ 90 nm technology to verify the proposed design.