Real-Time FPGA-Based Fault Tolerant and Recoverable Technique for Arithmetic Design Using Functional Triple Modular Redundancy (FRTMR)

摘要

Single Event Upset (SEU) is a serious issue when considering the real-time process for critical time constraint applications. Scaling of the devices, in complex computing devices is sensitive to transient faults. Transient faults are not permanent but it causes the critical issues in real-time applications by flipping its bits. The proposed technique is an approach toward improving fault tolerance of the field-programmable gate array (FPGA) for Single Event Upset (SEU) soft error. The technique uses the Functional Fault tolerance and Recovery Technique using the Triple Modular Redundancy (TMR). Functionality and reliability are tested on ALTERA Cyclone Ⅲ device by modeling 4-bit adder allow identifying and recovering soft error caused by Single Event Upset (SEU). The fault is injected and recovery time for the fault detection and restoring is less than 6 ns with the efficiency of 100% and 98% for single and multiple bit faults respectively.