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Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it
Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it
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机译:具有容错特性的通用纠错电路,以及应用该电路的解码器和三重模块冗余电路
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摘要
The present invention provides a universal error-correction circuit with fault-tolerant nature, and a decoder and a triple modular redundancy circuit that apply it, where the universal error-correction circuit with fault-tolerant nature includes: an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I 0 , I 1 ..., I 2 k -1 , and I 2 k , digital output signals of the error-correction unit with fault-tolerant nature are separately O 0 , O 1 ..., O k -2 , and O k -1 , and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to: when k=1, set O 0 = I 0 if I 0 = I 1 , and O 0 = I 2 otherwise; and when k1, set O k -1 = I 2 k -1 if O k -2 =I 2 k -1 , and O k- 1 = I 2 k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate. There may be a plurality of specific implementation manners, as long as input and output meet the uniquely certain logical relationship of the present invention. Therefore, the error-correction circuit with fault-tolerant nature provided by the present invention is provided with general commonality.
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机译:本发明提供了一种具有容错特性的通用纠错电路,以及应用该电路的解码器和三重模块冗余电路,其中,具有容错特性的通用纠错电路包括:带有故障的纠错单元由逻辑门实现的容错性质,其中具有容错性质的纠错单元的数字输入信号分别为I 0,I 1 ...,I 2 k -1和I 2 k,具有容错性的纠错单元分别为O 0,O 1 ...,O k -2和O k -1,数字输入信号和数字输出信号属于{0,1 },其中k是一个正整数。具有容错性质的纠错单元被配置为:当k = 1时,如果I 0 = I 1则设置O 0 = I 0,否则设置O 0 = I 2;当k> 1时,如果O k -2 = I 2 k -1,则设O k -1 = I 2 k -1,否则设O k-1 = I 2 k。因为输入和输出之间的逻辑关系是唯一确定的,所以具有容错性质的纠错电路可以仅通过逻辑门来实现。只要输入和输出满足本发明唯一确定的逻辑关系,就可以有多种具体的实现方式。因此,本发明提供的具有容错性的纠错电路具有通用性。
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