Lost Packet Retransmission Mechanism Based on Hardware Acceleration in Wireless Sensor Networks

摘要

As the continuous development of wireless sensor networks, the network has put forward higher requirements for the transmission of large amounts of data. In order to meet the high efficiency of network transmission, we often use various technologies to increase the transmission rate, but this may also cause high packet loss rate on the network. Therefore, in order to reduce the packet loss rate of the network, this paper proposes a lost packet retransmission technology based on reliable transmission of large amounts of data in wireless sensor networks. This technology is based on a multi-hop efficient transmission network platform composed of multiple wireless nodes. This is an FPGA-based lost packet retransmission mechanism that can make full use of the parallel processing capabilities of the FPGA to reduce the packet loss rate when transmitting large amounts of data. Finally, the experimental results show that this technology can guarantee the reliable transmission of large amounts of data in multi-hop transmission networks and has a lower packet loss rate.