Leakage Power Improvement in SRAM Cell with Clamping Diode Using Reverse Body Bias Technique

摘要

Leakage has been the main issue in SRAM design due to the scaling of CMOS devices. In this paper, a novel technique has been proposed for 8T SRAM to reduce leakage current at 45-nm technology node. Here, we have used three different reverse body biasing techniques to reduce the leakage power. The three techniques used are: clamping of NMOS diode, clamping of PMOS diode, and clamping of NMOS and PMOS diode. Out of the three techniques, leakage current in 8T SRAM was minimum using PMOS clamping diode as compared to other proposed techniques. The supply voltage has been varied from 0.5 to 0.85 V. The leakage current has been reduced by both NMOS and PMOS clamping techniques, but the results for PMOS and NMOS were high as compared to two but lower than that of SRAM cell. The leakage current improved by 3.3x using PMOS technique and 2.7x using NMOS technique at supply voltage of 0.5V. The static power has also been calculated and compared for the three techniques.