A hybrid ADC combining capacitive DAC-based multi-bit/cycle SAR ADC with flash ADC

摘要

This paper presents a new hybrid 8-bit analog-to-digital convertor (ADC) combining a capacitive digital-to-analog (CDAC) based multi-bit/cycle successive approximation (SAR) ADC with a flash ADC. We extract 4 bits of MSB's from two rounds of 2-bit/cycle SAR operation and another 4 bits of LSB's using flash ADC. By using the proposed scheme, we achieved not only high-speed conversion, but also more efficient digital-error-correction (DEC). The simulation results using 350nm CMOS technology, reveal that the proposed ADC saves capacitor size by 78% and boost the speed by 279%.