HDL DESIGN FOR ULTRA HIGH MULTI FREQUENCY CLOCK RATE-MULTI CHANNEL PRBS UNIVERSAL DATA SCRAMBLER DESCRAMBLER ASIC IP CORE

摘要

Scrambler De-Scrambler is a device used to encode and decode the message data in to randomized(Seed words) data.. This paper deals Design of High Speed Multichannel Universal Data Scrambler De-ScramblerOf Different Data Rates (Giga/Tera Bit Rate) for Ultra High Speed Wireless Applications like Gigabit WIMAX,WIFI,3G,4G,Parallel Data Computing, Internet, Cloud Computing etc. Scrambling Different PRBS Data as perCCITT - ITU Standards. This Design consists of Different Pattern Sequence based PRBS Generators & XOR Gates for encryption and decryption of digital data either serially/parallel. Design using Xilinx ISE 9.2i Software,Programming done by using VHDL & Verilog HDL, Design Implementation on Latest Xilinx Spartan III FPGA Kit.