Optimization of Holding Voltage for 5V Multi-Finger NMOS Using Voltage Stepping Simulation

摘要

For IC component designs, ESD is one of an important issue which has to be taken in consideration for reliability of a device. We use the TLP Voltage Stepping simulation scheme in Medici simulation for 5V NMOS Multi-finger structure, the use of silicon model and set of variables, in silicon material parameter is used to vary the variable electron and Holes parameters of silicon, which can make the Holding Voltage simulation change and to make the simulation and the silicon data more consistent. We have simulated and calibrated Holding voltage of 5V NMOS multi finger to match with silicon data.