首页> 外文会议>International Conference on Electronic Engineering and Information Science >Full Scan Structure Application in the Design of 16 Bit MCU
【24h】

Full Scan Structure Application in the Design of 16 Bit MCU

机译:全扫描结构应用在16位MCU的设计中

获取原文

摘要

A design project of 16 bit RISC MCU with full scan structure by the tool of SYNOPS YSTM DFT COMPILER. The flip-flops can be linked into the chains;;the memory modules in the MCU were tested by the technology of BIST;;and the circuits were tested by the test vectors by ATPG. The chip test circuit include 8 chains, and cover rate can reach at 99.20%.
机译:16位RISC MCU的设计项目,由SystM DFT编译器的工具具有全扫描结构。触发器可以链接到链中;; MCU中的存储器模块由BIST技术进行测试;;并且通过ATPG测试电路。芯片测试电路包括8个链,覆盖率可达99.20%。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号