Phenomena of Dielectric Capping Layer Insertion into High-κ Metal Gate Stacks in Gate-First/Gate-Last Integration

摘要

This paper presents systematic studies performed to investigate the properties of dielectric capping layers inserted in high-k metal gate stacks. Physical mechanisms involving such material systems are studied by using identical gate dielectric stacks of La inserted in HfO_2 and are studied in both gate-first and gate-last integration. The studies reveal a strong dependence on the thermal budget that the gate stacks are subjected to in forming the capping layer induced dipoles that in turn influences the dipole related threshold voltage shifts and lowered gate leakage. By varying the position of the capping layers in the HfO_2 gate dielectric, the threshold voltage and gate leakage are reduced by ~ 200mV and 1.5-2 orders of magnitude respectively in gate-last integration and ~580mV and 4 orders of magnitude respectively in gate-first integration.