Via-Last technology for the interconnection of flash and processor chip for mobile applications

摘要

Some mobile applications require non-volatile memory components and very small spatial dimensions. The development results presented in this paper are related to a via-last integration scheme where a standard flash memory is connected to the backside of a processor chip using through silicon vias. Special focus was given to the realization of chip interconnects including the required signal redistributions between processor chip and memory die. Most challenging part of this TSV process was related to the DRIE of the multilayer BEoL stack of the processor wafer. The TSVs applied within this project having a diameter of 20μm and depth of about 100μm After finishing TSV formation a two layer polymer RDL was applied. Within this process the copper TSV as well as the Al-metallisation of the standard contact pads were connected with the RDL. Additional interconnects were formed for FC-bonding of a second flash memory (optional) at the front site. After TSV formation and FS-RDL processing the wafer was flipped, temporary bonded, and grinded with stop above the TSV followed by TSVs revealed from the wafer backside. Finally a back site RDL and bump interconnects were applied. The flash memory has been assembled using a die-to-wafer technique. The individual 3D-Systems (processor and flash) have be tested and showed full functionality