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Finite Element Analysis of a High Voltage Semiconductor Polymeric Package Design using a Taguchi Based Experimental Design

机译:基于Taguchi的实验设计的高压半导体聚合物包装设计的有限元分析

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Plastic packaging has made successful progress in replacing ceramic and metal packages in many high reliability electronics applications where hermetic packaging has traditionally been used, e.g. military and aerospace semiconductors. However for high voltage/high current power devices, such as the thyristors and diodes used in High Voltage Direct Current (HVDC) power transmission applications, hermetic packaging is still the dominant technology. With increasing energy demands from large and rapidly developing countries, such as China, India, Brazil, etc., HVDC transmission is expected to play a significant role in meeting future current/voltage requirements and is consequently pushing suppliers to use larger semiconductor wafer diameters, thus requiring bigger, more fragile and more expensive packages. A switch from the present ceramic packaging to polymer packaging is expected to achieve a robust, low cost and low weight device. This paper reports a study of the design and electrical performance of a polymer package for high voltage devices using Finite Element Analysis (FEA) when blocking a high DC voltage. Following on from preliminary simulation studies where a number of design parameters were observed to influence the electrical field distribution within the package, the Taguchi Method of Experimental Design (TMED) has been used to systematically investigate the influence of design parameters on the electrical performance of the housing using a series of FEA simulations. For this work, the interactions between different design parameters were first identified and then used with the appropriate design factors to determine the optimum design settings, and to identify the contribution of the design factors towards the electric field variation. From the investigations, the copper pole piece diameter and package thickness were seen to have little effect on the electric field magnitude inside the housing, while factors such as the position and depth of the metal insert in the housing and the number of convolutes around the package, had a significant influence on the electrical stress magnitude.
机译:塑料包装在替代许多高可靠性电子应用中的陶瓷和金属包装方面取得了成功的进展,其中传统上使用了密封包装,例如,军事和航空航天半导体。然而,对于高电压/高电流功率器件,例如在高压直流(HVDC)电力传输应用中使用的晶闸管和二极管,密封包装仍然是主导技术。随着来自大型和快速发展中国家的能源需求,如中国,印度,巴西等,HVDC传输预计在满足未来电流/电压要求时发挥着重要作用,因此推动供应商使用较大的半导体晶片直径,因此需要更大,更脆弱和更昂贵的包装。预期来自本陶瓷包装的切换到聚合物包装,以实现坚固,低成本和低重量的装置。本文报告了使用有限元分析(FEA)在阻塞高直流电压时使用有限元分析(FEA)的聚合物包的设计和电性能的研究。在初步模拟研究之后,观察到许多设计参数来影响包装内的电场分布,实验设计(TMED)的TAGUCHI方法已被用于系统地研究设计参数对电气性能的影响外壳使用一系列FEA模拟。对于这项工作,首先识别不同设计参数之间的相互作用,然后与适当的设计因子一起使用以确定最佳设计设置,并确定设计因素对电场变化的贡献。从调查中,看到铜管件直径和包装厚度对壳体内的电场幅度几乎没有影响,而金属插入件的位置和深度诸如壳体中的圆形件和围绕包装周围的卷围的数量。 ,对电应力幅度产生重大影响。

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