Thermal behavior of stack-based 3D ICs

摘要

The 3D IC technology has attracted much interest in the recent past as a mean to efficiently improve performance and miniaturization of electronic integrated circuits (IC) [1]. The integration is based on three dimensional (3D) die stacking, connected thanks to Through Silicon Vias (TSV), μcopper pillars and large copper pillars. Although this approach offers several advantages in terms of electric features, the thermal management is widely identified as one of the key challenges [2].