Influence of a Deep NBL Structure on ESD/Latch-up Immunities in the Power Device nLDMOS

摘要

In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small R_(on) resistance, low trigger voltage (V_(t1)) and high holding voltage (V_h) characteristics. Here, we introduce a deep N~+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV structure processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.