The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as adders and multipliers. In this paper SERF and Modified SERF full adder topologies are presented. The analysis of Power, Delay, Power Delay Product (PDP) optimization characteristics of SERF Adder is designed. In order to achieve optimal power savings at smaller geometry sizes, proposed a heuristic approach known as Modified SERF adder model. The proposed Modified SERF adder model consumed the least power compare to SERF Adder with no deterioration in performance. Taken together, the results suggest that the Modified SERF Adder is well suited for ultra low power design and fast computation at smaller geometry sizes.
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