Minimization of Cascade Low-Noise Amplifier with 0.18 (mu)m CMOS Process for 2.4 GHz RFID Applications

摘要

The cascade LNA circuit adding parasitic capacitance (C_(p)) for neighboring passive inductors at 2.4GHz with low-cost and high-integration 0.18(mu)m CMOS process was designed and studied. The simulation results adopting an ADS software as a simulator demonstrated the forward voltage gain is 11.908dB, the input return loss is -9.563dB, the output return loss is -21.153dB, the reverse isolation is -16.315dB, the minimum noise figure is 2.01dB and the 3-dB gain bandwidth is 240MHz. Comparing the performance with C_(p) and without C_(p), we observed that they indeed had some change. The noise figure was slightly reduced and the voltage gain was increased a little. The benefit of chip size shrinkage was about 3percent. Totally, these interesting parameters still verify that this contrived LNA with ultra-low noise performance plus parasitic capacitance effect is still suitable to be a candidate in the whole receiver integration for RFID applications.