An on-chip jitter and skew measurement circuit has been presented. By using two delay lines and a single latch, the circuit measures the cumulative probability distribution due to jitter. By differentiating and using an on-chip delay calibration, the original distribution is recovered. In addition, use of a common time base for multiple placements of the circuit enables measurement of clock skew. The circuit has been demonstrated in stand-alone test sites for characterization, and has been used to measure the jitter and skew of an experimental clock network. It has a demonstrated resolution of less than 1 ps up to 2 GHz clock frequency.
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