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Feasibility study of EUVL for high volume production applying an electrical test chip - (PPT)

机译:EUVL对高批量生产的可行性研究应用电气测试芯片 - (PPT)

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We evaluated the feasibility of EUVL to high volume manufacture applying an electrical test chip. Following key technologies are investigated and proved to be just before mass production of 35 nm half pitch (22 nm technology-node). Imaging quality of exposure tool; Mask fabrication; Flare compensation methodology. Big yield gains were obtained by improving resist processes. 70% yield was obtained in 35 nm hp at 1000 mm length. 100% yield was obtained in 35 nm hp in 10 mm length. Yield was obtained in 32 nm half pitch. We, Selete and Toshiba, will collaborate to enhance readiness of EUVL both in 22 nm tech. node and beyond.
机译:我们评估了EUVL对高批量制造的可行性应用了电气测试芯片。调查并证明在批量生产35nm半间距(22 nm技术节点)之前,进行了以下关键技术。曝光工具的成像质量;面膜制造;耀斑补偿方法。通过改善抗蚀剂过程获得大产量提升。在35nm HP的35nm长度下获得70%的产率。在35nm HP的10mm长度中获得100%产率。在32nm半间距中获得产率。我们,Selete和Toshiba将在22纳米科技中加强EUVL的准备。节点和超越。

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