The verification of network processor Fast Bus Interface using SystemVerilog

摘要

According to the background of network processor XDNP, this article describes a design of Fast Bus Interface(FBI) verification platform based on VMM architecture. All of the components and codes in the verification platform are achieved by SystemVerilog and assertions are also used in the process of verification. Through resonable usage of SVA it bacomes much easier to check out errors occuring in the executive process of FBI quickly and exactly. And then, the valuable functional verification results are obtained.