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Verilog-A modeling and design of a micromachined capacitive accelerometer

机译:Verilog-微机械电容式加速度计的建模与设计

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摘要

In order to design accelerometers, electromechanical hybrid simulation with the sensor and interface circuit together is required. In this paper a Verilog-A model for the accelerometer sensor is presented, and based on the Verilog-A model presented, an open-loop capacitive accelerometer with a full-scale range of ±2g is presented. The Verilog-A model, characterizing the properties of the sensor, is compared to be right with the Matlab model published before. The accelerometer is tested to achieve the equivalent noise acceleration (ENA) about 7.7µg/√Hz.
机译:为了设计加速度计,需要使用传感器和接口电路的机电混合模拟。在本文中,A Verilog-A用于加速度计传感器的模型,并基于呈现的Verilog-A模型,提出了具有全尺度范围±2g的开环电容式加速度计。 verilog-a型号,表征传感器的属性,与之前发布的Matlab模型进行比较。测试加速度计以实现相当于7.7μg/√Hz的等效噪声加速度(ENA)。

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