Addition is an essential function in fundamental arithmetic operations. It is also the most copiously used operation in application-specific processors and digital signal processing application (DSP). In this paper, we propose a novel 17-transistors full-adder based on the N-12T full-adder, which has a maximum of one threshold voltage (V_t) degradation for output voltage levels. The performance of the proposed full-adder is compared against other low-power full-adder via extensive HSPICE simulation using 100 random input vectors. The simulation results show that the proposed design permits the use of lower operating voltage to derive lower power consumption and hence, the power delay product (PDP). The advantages of the proposed full-adder has been evaluated by integrating the proposed full-adder into a multiplier-less finite impulse response (FIR) filter that is commonly used in the multirate filter bank for biomedical applications.
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