A Case Study on Fully Asynchronous ACS Module of Low-power Viterbi Decoder for Digital Wireless Communication Applications

摘要

This paper proposes a novel low-power fully asynchronous ACS module of the Viterbi decoder to improve the shortcomings of low throughput and high power consumption in conventional synchronous ACS module. The computation quantity can be reduced by adopting pre-computation algorithm which can select the survival path ahead of time. We use null convention logic to implement the fully asynchronous circuits to reach-low power and delay-insensitive. These qualities allow the module working at the maximum speed environment permits, and meanwhile avoid performance degradation in conventional synchronous design brought by critical path. Results have demonstrated that the design proposal in this paper has a throughput improvement by 36.3% and a power consumption reduced by 30.1% over the synchronous one. The novel design is suitable for low-power wireless communication applications with the characteristics of glitch immunization, delay-insensitive and speed adaptive.