Speed, Noise Immunity, Power Consumption and Area Comparison between Different Approaches of Low-Power Viterbi Decoder for Digital Wireless Communication Applications

摘要

Noise immunity and speed are two vital issues for designing encoding-decoding system for wireless communication. Convolutional coding is widely used in wireless communication system for its error correction property. For the decoding purpose of Convolutional coding Viterbi decoder is used. Core module of Viterbi decoder is Adder-Comparator-Selector (ACS) which takes approximately 70% of total power consumption. So, Adder-Comparator-Selector (ACS) module is transformed into Comparator-Selector-Adder CSA) module for power saving. Reduction of Hamming Distance Logic Circuitry for branch metric calculation also saving power but enhances the packing density of the circuit. In this paper the comparison between ACS and CSA is not only described in terms of power reduction and area but also speed and noise immunity are compared. Basically there are three types of Viterbi decoders: namely Register Exchange, Shift Update and Selective Update. These decoders do not follows the parallelism and pipelining concept but folding cascaded designing of Viterbi Decoder supports parallelism which enhance the speed of the system. This paper gives a new idea of logic reduction of Viterbi Decoder as well as comparison of different Viterbi decoders in different aspects.