首页> 外国专利> Low-power state-sequential viterbi decoder for CDMA digital cellular applications

Low-power state-sequential viterbi decoder for CDMA digital cellular applications

机译:用于CDMA数字蜂窝应用的低功率状态序列维特比解码器

摘要

A method, apparatus, and a program storage device useful in performing computations to decode a convolutionally coded sequence without resorting the use of switching elements is disclosed. The method comprises the steps of computing a first branch metric between a first input node and an output node, adding a first input path metric to the first branch metric to produce a first candidate output path metric, computing a second branch metric between a second input node and the output node, adding the second branch metric to a second path metric to derive a second candidate output path metric, and configuring a decision bit based upon the parity of the output state node state and upon whether the first candidate output path metric is greater than the second candidate output path metric. In one embodiment, a comparison between the first and the second candidate output path metrics is compared to the parity of the output node by an exclusive OR gate or a table lookup to determine the decision bit. The invention also is described by an apparatus comprising a means for performing these steps and a program storage device tangibly embodying instructions to perform the steps.
机译:公开了一种用于执行计算以对卷积编码序列进行解码而无需借助开关元件的方法,装置和程序存储设备。该方法包括以下步骤:计算第一输入节点和输出节点之间的第一分支度量;将第一输入路径度量添加到第一分支度量以产生第一候选输出路径度量;计算第二输入之间的第二分支度量。节点和输出节点,将第二分支度量添加到第二路径度量以得出第二候选输出路径度量,并基于输出状态节点状态的奇偶性以及第一候选输出路径度量是否为大于第二候选输出路径度量。在一个实施例中,通过异或门或表查找将第一候选输出路径度量和第二候选输出路径度量之间的比较与输出节点的奇偶校验进行比较以确定判决位。本发明还通过一种设备来描述,该设备包括用于执行这些步骤的装置以及程序存储设备,该程序存储设备有形地体现了用于执行这些步骤的指令。

著录项

  • 公开/公告号US6163581A

    专利类型

  • 公开/公告日2000-12-19

    原文格式PDF

  • 申请/专利权人 THE REGENTS OF THE UNIVERSITY OF CALIFORNIA;

    申请/专利号US19980072654

  • 发明设计人 INYUP KANG;

    申请日1998-05-05

  • 分类号H03D13/41;

  • 国家 US

  • 入库时间 2022-08-22 01:06:07

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