Failure analysis in complex integrated microelectronic devices is of increasing importance to improve their reliability, quality, and manufacturing yield. Non-destructive testing methods for localisation of shorts and opens in the internal circuitry are required, particularly for complex and fully packaged devices. The method of Lock-In Thermography (LIT) was developed for localisation of electrically active defects on the Integrated Circuit (IC) level. LIT works on the principle of pulsing the supply voltage of the Device Under Test (DUT) with a specific "lock-in" frequency and measuring the thermal response. One significant advantage of this technique is its ability to detect hot spots with a small amount of dissipation power. Furthermore, this technique also allows non- destructive failure localisation inside fully packaged devices. Due to heat transport through the package material, a phase-shift occurs between the electrical input signal and the surface temperature signal. This phase-shift can be measured and used to determine also the depth of an inner defect. One main challenge is that due to the necessary heat transport through the non-IR-transparent package material, the measured temperature distribution has a lower amount of temperature change and a laterally spread temperature distribution, compared to an opened device. In earlier experiments, the influence of the lock-in frequency on the amplitude of the thermal response signal was investigated [1]. In our first calculations, defect depths are determined with Finite Element (FE) modelling, using a measured phase-shift and known device geometry. In addition, the applied lock-in frequency can be optimized getting best possible thermal detection sensitivity and lateral resolution. A higher frequency permits better spatial resolution and therefore better defect allocation, but suffers from a lower signal-to-noise ratio. The signal-to-noise ratio and the resulting limitation of measuring the phase-shift is especially important and the main reason for using thermal simulations. In many cases, the resulting phase-shifts are calculated by thermal simulations in a shorter time than can be determined in an experiment. In the future, FE simulations could be used to determine the optimal lock-in frequency for the measurement. In this paper thermal spreading in lock-in processes were calculated using finite element modelling and compared with LIT measurements on test samples. The investigations should help to understand the relationship between defect depth and resulting phase-shift. The results served as the input for the next step, wherein a stacked-die package containing two chip layers was modified, generating defects within each layer. LIT was used to measure the phase signal determining the defect depth.
展开▼
