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Design of A 100MHz 64-Point FFT Processor in 0.35μm Standard CMOS Technology

机译:在0.35μm标准CMOS技术中设计100MHz 64点FFT处理器

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applications such as digital spectrum analyzers, digital filtering, image processing, and video transmission need to compute the Discrete Fourier Transform (DFT) A Chip architecture to compute a 64- point DFT using radix-4 algorithm every 18.87 μs at 100MHz clock rate is designed. This processor incorporates static memory, controller, and combinational operating unit (COU). Input data and output data are 10-bit and 54-bit words, respectively. A 10-bit × 27-bit multiplier is used inside the processor. Two's complement is used to present negative data. This processor is implemented in 0.35μm tsmc standard CMOS process.
机译:数字频谱分析仪,数字滤波,图像处理和视频传输等应用需要计算离散傅里叶变换(DFT)芯片架构,以在100MHz时钟速率下每18.87μs使用基数-4算法计算64点DFT 。该处理器包括静态存储器,控制器和组合操作单元(COU)。输入数据和输出数据分别是10位和54位字。在处理器内使用10位×27位倍增器。两个的补充用于呈现负数据。该处理器以0.35μm的TSMC标准CMOS过程实现。

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