Pipelined Residue Logarithmic Numbers System for general modules set {2n-1, 2n, 2n+1}

摘要

In this paper, we study residue logarithmic numbers system and design pipelined arithmetic logic unit for Residue Logarithmic Numbers System in order to be used for module set {2n -1,2n ,2n +1} that leads to implementation of integrated circuits for the general module with high speed and security but low power consumption. In this design a combination of two Logarithmic Number System and Residue Numbers System are used in order to design an arithmetic logic unit which uses characteristics of these two systems. In this system for addition and subtraction operations of arithmetic logic units, we use modified CRT instead of suggested MRC in naivi method and also we use direct transform for changing weight numbers to residue numbers and then we perform the modules addition circuits in third suggested stage by using Carry Select Adder. VLSI tools also are used for comparison and simulation. Results of these comparison and simulations show the suggested design ability for speed of integrated circuits. Part two introduces Logarithmic Number System and Residue Numbers System. Part three introduces add logarithm in numerical system of RLNS. Part four introduces suggested design for addition and subtraction circuits, Part five provides a comparison of previous methods with suggested method and part six provides conclusions.