Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks

摘要

The BurstMode?? test clocking methodology, first presented in [8], is improved to handle circuits with synchronous clocks of different frequencies. An on-chip clock controller allows to select a large number of clock waveforms necessary to test synchronous cross-domain paths at-speed and control supply voltage variations. The methodology is applicable to both ATPG and BIST and only requires combinational analysis tools. The methodology is applied to a large circuit to adjust power supply margins of an at-speed BIST test.