A quasi two-dimensional conduction model based on the thermionic emission of charge carriers over the energy barriers at discrete grain boundaries is proposed. The grain boundaries are characterized by an energy-dispersed density of trap states and a conduction model is formulated for a polycrystalline silicon thin-film transistor with an intrinsic channel. A “line” charge is formed adjacent to the interface of the channel and gate dielectric of the transistor by the occupied trap states and the electrostatic potential of a grain boundary is subsequently determined. This general approach allows the modeling of energy barriers for a transistor with an intrinsic channel and the resulting conduction model is continuously applicable from the “pseudo sub-threshold” to the ‘linear’ regime of operation of a transistor.
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