A 76 dBΩ, 2mW, 10Gbps Optical Receiver Analog Front-end in 80nm CMOS

摘要

This paper describes the design of an optical receiver analog front end for a low power, high speed, chip-to-chip or board-to-board communication system. The circuit has been designed in 80nm CMOS and consumes 2mW with a 1-V supply. Using active inductors, a transimpedance gain of 62.5 dB-Ω,limiting amplifier gain of 15dB, and overall bandwidth of 9GHz was achieved. This work presents the highest gain-bandwidth product and lowest power consumption for optical front-end receivers in this process reported to date.