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Optimisation of a Geiger Mode Avalanche Photodiode Imaging Pixel based on a hybrid bulk SOI CMOS process

机译:基于混合体SOI CMOS工艺的地革命模式雪崩光电二极管成像像素的优化

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Single photon detection has a wide variety of scientific and industrial applications including optical time domain refiectometry, astronomy, spectroscopy, defect monitoring of Complementary Metal Oxide Semiconductor (CMOS) circuits, fluorescence lifetime measurement and imaging, In imaging applications, the dead time is the time during which the detector is inhibited after a photon has been detected. This is a limiting factor on the dynamic range of the pixel. The rate of photon detection will saturate if the dead time is too large, Time constants generated by Metal Oxide Semiconductor (MOS) transistor bulk and sidewall capacitances adversely affect the dead time of pixels developed in conventional CMOS technology In this paper, a novel imaging pixel configuration based on a Geiger Mode Avalanche Photodiode (GMAP) and fabricated using a dedicated hybrid bulk Silicon On Insulator (SOI) CMOS process is presented. The GMAP is fabricated in the bulk layer and the CMOS circuitry is implemented in the upper SOI layers, As a result, bulk and sidewall capacitance effects are significantly reduced. As both the diode and the CMOS transistors are on the same wafer there is a reduction in pixel area and an additional reduction in the parasitic capacitance effects. This leads to a significant improvement in pixel performance Pixels incorporating 5 micron and 10 micron diameter GMAPs have been simulated The circuits were optimised with a view to maximising the photon count rate. Results show a significant improvement in the dead time with values of 14 nanoseconds and 15 nanoseconds being observed for the 5 micron and 10 micron GMAPs respectively.
机译:单光子探测有各种各样的科学和工业应用中,包括光时域反射计,天文学,光谱学,缺陷监测互补金属氧化物半导体(CMOS)的电路,荧光寿命的测定和成像,在成像应用中,死区时间的时间在此期间,已经检测到的光子后的检测器被禁止。这是像素的动态范围的限制因素。如果死区时间过大光子检测的速率将饱和,由金属氧化物半导体(MOS)晶体管的体积和侧壁电容产生的时间常数的像素在常规CMOS技术开发在本文中,一种新颖的成像像素的死区时间产生不利的影响基于盖革模式雪崩光电二极管(GMAP),并使用专用的混合块状绝缘体上硅(SOI)CMOS工艺制造的配置被呈现。该GMAP是在体层制造和CMOS电路在上部SOI层中实现,其结果是,体积和侧壁电容效应显著降低。作为二极管和CMOS晶体管都在同一晶片上,存在像素区域的减小和寄生电容效应的额外减小。这导致在将5微米和10微米直径GMAPs像素性能像素的显著改善已被模拟的电路进行,以最大化光子计数率最佳化。结果表明,对于5微米和10微米Gmaps的14纳秒和15纳秒的值显示出的死区时间显着改善。

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