The Design and Implementation of a Reconfigurable USART IP Core for Embedded Computing With Support for Networks

摘要

Embedded systems have drastically grown in importance and complexity in recent years. Many systems are now designed using Field Programmable Gate Array (FPGA) due to its size, flexibility, and resources. This paper presents the design and implementation of a flexible and user reconfigurable Universal Synchronous Asynchronous Receive Transmit (USART) IP core suitable for use in embedded systems and Systems on Chip (SoC). The design scheme employed allows the USART to be used in various modes of operation such as standalone and 9-bit addressable mode for multi-drop networks. It also supports high speed data rates of up to 3 Mb/s. The design utilizes Hardware Description Language (HDL) to describe the operation, ease implementation and allow cross platform utilization. The paper shows through comprehensive testing that the proposed design functions properly while consuming minimum resources from the target FPGA.