Design and Optimization of ÷8/9 Divider in PLL Frequency Synthesizer with Dynamic Logic (E_TSPC)

摘要

Selection of dynamic dividers in CMOS PLLs for GHzs applications allows remarkable reduction in power loss without affecting phase noise and power supply sensitivity. Frequency dividers are combination of classic TSPC logic (true-single-phase-clock) and E_TSPC logic (extended TSPC). The designed PLL with % 8/9 prescaler is used for wireless LAN applications and synthetic of frequencies between 5.14 to 5.70 GHz. In this paper a % 8/9 prescaler has designed at 0.25 micrometers process for 2.5-3 GHz band width. This prescaler has been designed with 2.5v power supply with using E_TSPC logic. In this circuit in addition to decrement of power consumption, divider can work in a nearly high speed. Subsequently the dimensions of transistors have been improved and power consumption has been reduced from 3.8 mw to 2.9 mw. Then, the layout of circuit has been designed with L-Edit software. The simulation results of are identical to that we expect according to earlier Spice simulations.