Analysis of Timing Jitter in Inverters Induced by Power-Supply Noise

摘要

This paper describes the transformation process of power-supply noise (PSN) to timing jitter of inverters. The focus is on the inverters used in multiphase clock-generator circuits (CGCs) commonly needed for Switched-Capacitor (SC) Sigma-Delta (ΣΔ) Analog-to-Digital Converters (ADCs). Closed form expressions relating timing jitter and PSN are presented and the results are compared with Monte-Carlo simulations performed in Spectre at BSIM3v3 transistor model level using the processes AMS 0.35μm and UMC 0.18μm. The PSN is assumed to have a white frequency distribution with independent power and ground noise. The results show that the transformation process is approximately linear and that the jitter impact decreases as transistors move deeper into the submicron domain. Furthermore, the transformation process is not symmetrical and is dependent on switching direction, even if the PMOS and NMOS sizings are such that the effects due to difference in hole and electron mobility are mitigated.