Direct Wafer and Die Bonding Technology Applied to 3D Integration on Silicon: Recent results at LETI

摘要

3D integration technology is nowadays investigated in all microelectronic device fabrication steps. Semiconductor layers, transistors, wafers and chips are piled up in order to create new functionalities, enhance device performance or develop system on a chip. For that, 3D integration technology brings them together in one chip die, although they are processed on separated wafers [1, 2]. Reduction of package size and package cost implies development of through wafer interconnect structure. To bond wafers or chip together, flip-chip technology or polymer adhesive layer have been extensively used [3, 4]. Anyway direct molecular bonding combines enough advantages to be adapted for these applications such as: compatibility with front-end requirements and microelectronic process, possible monitoring of the thickness bonding layer (from few nm to few microns), low temperature process; through interconnect layer compatibility etc… We have developed a low temperature bonding process that combines deposited oxide, planarization and alignment (if needed). Several devices fabrication using this 3D integration technology will be presented.