Low power Adiabatic Logic based on 2PC2AL

摘要

This paper presents a new adiabatic circuit based on the 2-Phase Clocked CMOS Adiabatic Logic (2PC2AL). By adding two logic switches between the power supply and charging-discharging transistor, it can prevent the floating of the nodes and avoid unnecessary energy loss. In this paper, we apply the proposed adiabatic logic circuit to a 4×4-bit multiplier in the LTspice by using a 0.18 μm standard CMOS process. The simulation results show that the function of circuits can be realized and the power consumption can be reduced greatly compared to the CMOS circuit when the frequency ranges from 100 Hz to 100 MHz.