Prediction of Power Supply Induced Jitter in DDR Interfaces

摘要

This paper proposes a method to analyze and predict the power supply induced jitter (PSIJ) on data eye caused by both PHY core supply and I/O supply in DDR interfaces. Apart from predicting power supply induced edge TIE jitter of an individual data signal using extracted jitter sensitivity and power noise profile, the impact of jitter tracking effect and edge slope modulation on final data eye jitter is also considered by developing an analytical model. The accuracy of predicted data eye jitter is verified by simulation and measurement in an LPDDR4-3000 interface. An overall error of less than 20% is observed.