The PCIe Gen5 channel data-rate of 32GT/s requires a better mating connector, an AIC with improved PCB materials, optimized vias, and alternative trace routings. The Gen5 surface-mount connector mates with the smaller gold edge-fingers with a shorter wipe distance to achieve loss and crosstalk targets at twice the Gen4 Nyquist frequency. AIC microstrip or stripline routings, via choices, ac capacitor mounting, and their effects are optimized for overall channel performance. AIC lead-in trace region to the connector is re-designed to improve the impedance match to the CEM connector. Measurements of a connector prototype with improved AIC validate the work.
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