PDN Complexities Design Strategy for Serdes Interfaces in Automotive/Workstation Applications

摘要

High bandwidth data transfer requirement for automotive and workstation platforms is increasingly getting challenging for Power Delivery Network (PDN) design, especially with serdes interfaces. Pre-silicon budget of voltage margin for serdes interface supplies should factor in multiple factors such as process, temperature, DC drop and switching noise across chip, package and PCB. Budgeting should also be cognizant of the minimum voltage required to meet timing for digital blocks of serdes interfaces and their controllers. This paper discusses accounting of voltage budget parameters which aids with selection of minimum voltage corners to meet timing requirements. Noise evaluation from NVidia's platforms including die, package and PCB are discussed. Requirements and challenges focusing on PDN design for high speed serdes interfaces are elaborated. Simulation to measurement correlation from functional platforms are presented.