Modeling System Signal Integrity Dynamic to Achieve Optimal Memory Performance for DDR4 and Beyond

摘要

System memory performance is usually measured by the memory bandwidth, which is the speed of the memory IO interface (such as 3200Mbps for top speed DDR4) multiplied by the number of DQ signal that a system will support (such as 64 DQ bits). In addition to the bandwidth, the capacity of the memory system is also an important figure of merit. Memory array density in each DRAM is limited, therefore, multiple ranks and multiple DIMMs are often added to the system to increase system memory capacity. The effectiveness of quantifying memory bandwidth will need to take into account the actual data throughput. When a system has multiple ranks, the dynamic between the ranks is more complicated. Memory controller can issue a Read/Write from/to the same rank or from/to a different rank. Traditionally, empirical measurement from a real system can be tested to determine the optimal bus turnaround. This turnaround time is for the bus signal to settle. A violation will affect channel timing such as the pre-amble timing & causes data error. The turnaround time will directly impact the system effective bandwidth. The bandwidth efficiency is measured by the data throughput versus the total transaction duration. The efficiency will be estimated incorrectly if not considering the actual bus channel settling time of the system. This paper will present a modeling approach to cover the dynamics of system DDR bus turnaround. The DQ bus on the controller side and the DRAM is modeled with IO behavioral model which captures the On/Off timing. The On/Off states represent the driver mode and receive mode with on-die termination enabled. Details will be presented on how to handle the necessary feature for the modeling. This approach enables the prediction of bus channel dynamics, particularly in the case of turnaround signal integrity analysis. The method can equally apply to more complicated system configurations, such as multiple-rank DIMM systems, which often need to cover rank-to-rank switching between DIMMs. A validation system will be used to correlate this approach and will be presented in the paper.