A methodology for chip level power integrity analysis is presented. The approach accurately estimates the jitter induced on a victim block due to the current of an aggressor block through the power distribution network and linear voltage regulators. The analysis relies on simple stand-alone simulations of different blocks while the system-level analysis is completed by combining the results analytically. This procedure allows different designers to perform fewer and quicker simulations and as a result, there can be many iterations of the power integrity analysis to find the optimal solution. For example, the analysis can drive decisions regarding die capacitance partitioning and/or requirements for regulation on various circuit blocks.
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