Phase noise optimization of CMOS VCO through harmonic tuning

摘要

An optimization technique for a low phase noise CMOS LC VCO is proposed. The combination of harmonic tuning and on-chip filtering improves both 1/f/sup 3/ and 1/f/sup 2/ phase noise more than 10 dB over a comparable reference VCO. A 2.7 V, 5.4 mA, 30% tuning range, 1 GHz voltage controlled oscillator (VCO) is designed with the technique and implemented in a 0.35 /spl mu/m CMOS process. The optimized 1 GHz CMOS differential VCO achieves -89 dBc/Hz, -116 dBc/Hz and -135 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset frequencies from the carrier, respectively.