A System-Level SoC Design Methodology based on Multi-Languages

摘要

This paper presents a new SoC design methodology based on UML, SystemC and SystemVerilog to cope with the continuously increasing complexity of modern System-on-Chip (SoC). The methodology uses UML to describe the system requirements and overall architectures, SystemC to model and validate SoC at system level, and SystemVerilog to describe system behavior and structure at Register Transfer Level (RTL). This approach can increase the design abstract level and reduce design complexity. The paper puts emphasis on the basic design idea and design flow of the new methodology. Some key problems and corresponding solutions are discussed.