A New Domino Failure Mechanism in Deep Sub-100nm Technologies and Its Solution

摘要

The domino circuit failure is due to competing requirements of the keeper and the NMOS logic transistors that cannot be satisfied simultaneously in order to achieve the noise margin and performance objectives. Domino keeper transistor has to be, upsized to compensate for the subthreshold leakage and gate leakage currents that discharge the dynamic node in deep sub-100nm technologies. Domino multiplexer can fail when the fan-in number is greater than 14 for the noise margin of 0.1 Vdd, where the noise margin is defined as the input voltage that causes 10% voltage drop at the dynamic node of Domino. In simulation, 45nm BSIM4 models were used with the power supply voltage of 0.8V. To solve this problem, we propose a dual gate oxide thickness (Tox) implementation for high fan-in Domino. With proper dual gate oxide thickness assignment, subthreshold leakage and gate leakage that discharge the dynamic node are suppressed with the keeper size reduced. Proposed circuit not only prevents the possible failure in high fan-in Domino, but also reduces the delay and power consumption due to decreased contention between the keeper and NMOS logic tree. For 14-bit domino multiplexer, proposed circuit is 56% faster with 66% less power consumption and without area penalty, compared to single Tox domino.