A Standard Cell Based Power-Delay-Area Efficient 3-of-5 Majority Voter Design

摘要

This paper proposes a new standard cell based design for the 3-of-5 majority voter meant for use in quintuple modular redundant hardware. The voter can tolerate up to two faulty or erroneous inputs, and when a majority of the inputs are correct guarantees the production of the correct output. In comparison with the existing design of the 3-of-5 majority voter, the proposed design reports an increase in the figure-of-merit by 33.7%, where the figure-of-merit is defined as the inverse of the product of power, delay, and area. The results are based upon simulations, performed by targeting a 32/28nm CMOS process.