FPGA Realization of Hybrid Carry Select-cum-Section-Carry Based Carry Lookahead Adders

摘要

FPGA based synthesis of conventional carry select adders, carry select adders featuring add-one circuits (binary to excess-1 code converters), carry select adders sharing common Boolean logic term, hybrid carry select-cum-carry lookahead adders, and hybrid carry select-cum-section-carry based carry lookahead adders are described in this paper. Seven different carry select adder structures corresponding to 32 and 64-bit addition were described topologically using Verilog HDL, and were subsequently implemented in a 90nm FPGA (Spartan-3E). The results obtained show that the carry select adder utilizing section-carry based carry lookahead logic encounters minimum data path delay among all its counterparts.