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CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode

机译:CL-CPA:用于低功耗或高性能操作模式的混合超前/进位传播加法器

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In this paper, we present a double-operating-mode adder which may be employed either in low-power (LP) or high-performance (HP) operating mode. The adder has a hybrid structure based on a carry-lookahead and carry-propagate structures and hence is called CL-CPA. The selection between the two operating modes is performed through a mode selection bit during the operational period. The hybrid structure of the adder provides the feature of selecting the operating mode depending on the application deadlines and system available energy resources. The adder structure is realized by modifying the carry look-ahead tree (CLT) structure and then combining it with a carry propagate adder (CPA). During the LP mode, only the CPA structure is utilized while the CLT is deactivated through the power gating scheme. On the other hand, during the HP mode, the CLT structure is activated and the adder performs with its highest speed and power consumption using both CLT and CPA structures. The efficacy of the proposed hybrid adder is assessed by comparing its speed, power, energy, and area parameters with those of the other conventional adders obtained using HSPICE simulations for a 45-nm CMOS technology in a wide range of supply voltages. The results revel switching from the LP to HP operating mode leads to about 5.4X decrease, 2.5X increase, and 2.1X decrease in the delay, power, and energy of the 64-bit CL-CPA, respectively, averaged over the supply voltages. Also, the proposed hybrid adder provides flexibility on speed and power with an acceptable area usage for applications where both high speed and low power adders are required.
机译:在本文中,我们介绍了一种双工作模式加法器,它可以在低功率(LP)或高性能(HP)工作模式下使用。加法器具有基于超前进位和进位传播结构的混合结构,因此被称为CL-CPA。在操作期间,通过模式选择位可以执行两种操作模式之间的选择。加法器的混合结构提供了根据应用程序截止日期和系统可用能源选择运行模式的功能。加法器结构是通过修改进位超前树(CLT)结构,然后将其与进位传播加法器(CPA)组合而实现的。在LP模式下,只有CPA结构被利用,而CLT通过电源门控方案被停用。另一方面,在HP模式下,CLT结构被激活,加法器同时使用CLT和CPA结构以其最高的速度和功耗来执行。通过将其速度,功率,能量和面积参数与使用HSPICE仿真获得的其他常规加法器的速度,功率,能量和面积参数进行比较,可以比较该混合加法器的功效,该HSPICE仿真是针对45-nm CMOS技术在很宽的电源电压范围内进行的。从LP切换到HP工作模式的结果显示分别在整个电源电压上平均降低了64位CL-CPA的延迟,功率和能量,分别降低了5.4倍,2.5倍和2.1倍。 。而且,对于需要高速和低功率加法器的应用,所提出的混合加法器提供了速度和功率的灵活性以及可接受的面积使用。

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