A novel configurable frequency synthesizer based on delay-locked-loop (DLL) is presented in this paper, with maximum multiplication factor 10 and maximum division factor 16. A SRAM is employed to store configuration data for different multiplication and division factor. Users only need to change the data stored in the embedded SRAM to obtain frequency needed. The output frequency range is from 25MHz to 1GHz using tsmc 0.18μm CMOS process parameters. The locking time of the DLL core is 20 μs at 100MHz and 120μs at 25MHz. The cycle-to-cycle jitter of the DLL is 60ps. The circuit can be part of a standard digital cell library and can easily be used in field programmable gate array (FPGA).
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